Design-for-testability (“DFT”) techniques based on scan and automatic test pattern generation (“ATPG”) are commonly used as part of integrated circuit manufacturing to provide high test coverage. For large circuits, however, the volume of test data required to test such circuits can cause a significant increase in test time and tester memory requirements. In order to cope with these challenges, various test data reduction schemes have been introduced. Some test data reduction schemes, for example, use on-chip decompression and compression hardware. By using such hardware, a tester can deliver test patterns in a compressed form, and the on-chip decompressor can expand (or decompress) the compressed test patterns into the actual data loaded into scan chains. The decompression operation is possible because typically only a small number of bits in the decompressed test patterns are specified bits designed to target one or more specific faults in the integrated circuit. The remaining unspecified bits of the decompressed test pattern are termed “don't care” test pattern bits and are typically randomly determined as a result of the decompressor structure. The high number of randomly filled test pattern bits, however, can cause excessive switching in the scan cells of the scan chains as the decompressed test pattern is loaded. This, in turn, leads to undesirably high power consumption during the test procedure.
Similarly, the test responses that are captured after the test patterns have been loaded into the scan chains and launched into the system logic often contain many test response bits that are not indicative of either the presence or the absence of any targeted fault. Because these test response bits do not contribute to fault detection or diagnosis, such test response bits can be termed “don't care” test response bits. As with the “don't care” test pattern bits, the “don't care” test response bits can also cause excessive switching in the scan cells of the scan chains when the test response is captured and/or when the test response is shifted out of the scan chains.
In D. Czysz, G. Mrugalski, N. Mukherjee, J. Rajski, J. Tyszer, “Compression based on deterministic test vector clustering of incompatible test cubes,” Proc. ITC, paper 9.2, 2009, which is hereby incorporated herein by reference, a test data compression scheme was introduced that explores the occurrence of similar vectors in test stimuli. In such a test data compression scheme, test cubes that share many similar specified bits are merged even in the presence of conflicts to increase the encoding efficiency and the compression ratio. The test vector obtained after merging is referred to as a parent pattern. To recover a test pattern from the parent pattern, the location and value information of conflict bits for this particular pattern is needed. The location information is stored in a set of data called the control pattern, while the value information is stored in another set of data called the incremental pattern. Like parent patterns, control patterns and incremental patterns are compressed before delivery to a circuit under test. Accordingly, the decompressor usually includes three decompressor modules/units for decompressing parent, incremental and control patterns, respectively, and combination circuitry for combining parent patterns and incremental patterns based on control patterns. Such a deterministic compression of incompatible test cubes offers very high compression ratios, elevates the encoding efficiency, and preserves all benefits of continuous flow decompression. The scheme, however, may consume more power than the power limit for which a circuit-under-test is rated. This power consumption is primarily attributed to the switching activity during the scan chain loading, capturing, and/or unloading processes that may go well beyond that of the functional mode.
The excessive power used during the scan chain loading, capturing, and/or unloading processes can result in overheating or supply voltage noise, either of which can cause a device to malfunction, be permanently damaged, or exhibit reliability degradation due to accelerated electro-migration. Accordingly, improved methods and test architectures for reducing power consumption during testing are desired.